parasitic capacitance
英 [ˌpærəˈsɪtɪk kəˈpæsɪtəns]
美 [ˌpærəˈsɪtɪk kəˈpæsɪtəns]
网络 寄生电容; 寄生電容; 杂散电容
双语例句
- In addition, as the result of optimizing ALU, system resources are saved and parasitic capacitance is minimized, and the aim of reducing power consumption is achieved accordingly.
另外，通过对算术逻辑单元进行优化设计，节省了系统的资源，减小了电路的寄生电容，从而达到了降低功耗的设计目标。 - The parasitic capacitance of the high speed laser is one of those factors which affect the modulation bandwidth.
高速激光器的寄生电容是影响其调制带宽的因素之一。 - A semi analytical integration approach applied in3 D multiple media interconnect parasitic capacitance computation with BEM is presented.
导出了一种解析积分算法，精确计算了二维各向异性位势问题边界元法中近边界点的几乎奇异积分。 - One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
有覆盖金属层或阱区时，须考虑寄生电容。 - Poor layout due to its sensitivity to parasitic capacitance, device mismatching, process variations and gradient errors will result in both the product inaccuracy and yield loss.
且由于敏感的寄生电容效应、元件的不匹配、制程变动与梯度效应都将导致布局结果可能是一个不好的布局，也造成了产品的不准确性与良率的降低。 - New VDMOS Structure with Reduced Parasitic Capacitance
一种减少VDMOS寄生电容的新结构 - Sometimes, just putting your finger on a clock trace adds enough parasitic capacitance to retard the clock edges.
有时候，只是将手指放在时钟轨迹上，加上足够的寄生电容来延迟时钟沿。 - The structure can reduce the parasitic capacitance of the sensor, improve the negative resistance characteristics of the sensitive film, and be used in micro gyroscope.
该结构降低了器件的寄生电容，改善了敏感薄膜的负阻特性，适用于共振隧穿效应陀螺。对共振隧穿效应陀螺进行了结构设计和理论仿真； - A novel configuration of a MOS varactor is designed for good linearity of Kvco, as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron.
通过改变MOS变容管的接入方法实现了更好的压控增益线性度，并采用了新的低寄生电容、低导通电阻的数控电容阵列结构来补偿工艺变化带来的频率变化。 - This may be caused by many factors, and the parasitic capacitance of IGBT is proved to be the key by the experiment and the analysis.
通过实验和理论分析可以证明，其主要起因是IGBT的寄生电容。 - Charge amplifier based on operational amplifier was used to eliminate influences of the parasitic capacitance.
采用电荷放大嚣作为电容-电压转换电路，来去除传感器本身以及传输导线引起的寄生电容的干扰。 - Parasitic capacitance and time delay for the interconnect in VLSI circuits at room temperature and 77 K are numerically simulated.
用数值计算方法详细模拟了室温及低温（77K）下VLSI电路中金属互连线的寄生电容和时间延迟，得到了金属互连线的几何结构对寄生效应的影响。 - The parasitic capacitance and resistance can be got from the processed real part and imagery part of the frequency response.
对频率响应实部和虚部的处理，可以得到寄生电容和寄生电阻等一些关键参数值。 - In the second part, we introduce the advantages of SOI devices together with their corresponding mechanisms: free of latch-up effect, low parasitic capacitance, easy to form shallow junctions and so on.
论文的第二部分介绍了SOI器件的优点：无latch-up效应，较低的源漏寄生电容以很容易形成浅结等，并对具体的机理作出了相应的解释。 - In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.
对互连寄生电容提取的研究背景进行了简要的介绍。 - This sensor is non intrusive in pipe. The influence of stray capacitance and parasitic capacitance have been eliminated by means of combining sensor parts and measuring circuits together, so the stability and precision have been improved greatly.
该传感器是非插入式，传感部件与测量电路集成一体，排除了寄生电容和杂散电容的影响，使测量精度和稳定性大大提高； - A HEMT small-signal equivalent-circuit model is introduced in this paper. Considering the difference between HEMT and MESFET, a method of extracting series-resistance, parasitic inductance, parasitic capacitance and intrinsic element parameters for HEMT small-signal equivalent-circuit is described.
本文用HEMT小信号等效电路模型，考虑到HEMT与MESFET结构上的不同点，具体分析了HEMT小信号等效电路中串联电阻、寄生电感、寄生电容和本征元件参数的提取方法。 - The noise performance and impedance matching are optimized with RF input parasitic capacitance in consideration.
在考虑输入寄生的前提下，对射频输入端的阻抗匹配和噪声性能进行了优化； - The LNA design method which absorbs the parasitic capacitance of ESD is introduced and compared with the traditional design method.
同时提出了将ESD的寄生电容吸收到LNA输入匹配网络中的设计方式，并与传统的计算方式做了对比。 - But for the structure reasons of the inductor windings, there is parasitic capacitance inside the inductor.
但是，由于电感线圈的结构原因，有大量的寄生电容存在于电感器内部。 - The parasitic capacitance is also discussed. One-port lumped parameters equivalent circuit model is then found based on above analysis.
并对寄生电容量进行了讨论，在此基础上，得出了可变电容的单端口等效电路模型。 - Because of parasitic capacitance, production technology, output of measure circuit and capacitance are non-linear, capacitive sensor measurement range has been greatly restricted.
但由于寄生电容，生产工艺，电容检测电路输出信号与电容大小呈现非线性等影响，使得电容式传感器的分辨率和测量范围受到很大的限制。 - The previous parasitic capacitance model, with the conformal mapping method can only solve the parasitic capacitance of common MOSFET, the results used to the high k gate MOSFET directly require correction factor to correct the results.
以往求解寄生电容的模型，用保角变换的方法和数值法只能求解普通栅MOSFET的寄生电容，将结果直接应用到高K栅MOSFET中，必须要添加修正因子才能与仿真结果一致。 - Considering the parasitic capacitance and distributed capacitance of the capacitance sensor, we use precision capacitance detection circuit and improve accuracy of the capacitive detection.
考虑到电容传感器的寄生电容和分布电容，采用精密的电容检测电路，提高电容检测精度。 - In the design of sensor probe, the guard ring technology and driven-cable technology were used to avoid the effect of the fringe field and the generation of parasitic capacitance.
在传感器探头的设计中，采用保护环技术及驱动电缆技术来避免边缘电场的影响和寄生电容的产生。 - From the perspective of EMI, this greatly increased the common-mode interference which aroused from charging and discharging parasitic capacitance from the traction inverter and the motor to the ground ( namely common-mode EMI).
从电磁干扰的角度看，这大大增加了通过牵引逆变器和电机对地的寄生电容进行充放电而产生的共模干扰。 - First, this paper analyzes the structure of the solar cell and photovoltaic array. It proposes the mathematical transmission-line model of the photovoltaic array considering the parasitic capacitance. The frequency characteristics of the equivalent model are analyzed.
本文分析了光伏电池和光伏阵列的结构，给出了考虑光伏寄生电容的光伏阵列传输线模型，分析了等效模型的频率特性，最后给出了测量结果。 - With scaling down of feature sizes of chips, the electrical resistance and parasitic capacitance have become a major factor that limits the performance of chips.
随着芯片特征尺寸的降低，金属互连中的电阻和寄生电容成为限制芯片性能的一个主要因素。 - And a high-frequency simulation modeling circuit is established with them. Using SABER software simulates the circuit, analysis the effects of passive circuit parasitic, the IGBT collector of heatsink parasitic capacitance parameter to common mode interference and differential interference.
使用Saber软件模拟仿真，对比分析了电路中的无源寄生参数、IGBT集电极对散热片的寄生电容等参数对差模干扰和共模干扰的影响。 - The output current, output voltage and dead time were analyzed with respect to the change of incident light intensity and frequency, reverse bias voltage, load resistance and parasitic capacitance.
通过改变模型中入射光强度和频率、反向偏置电压、负载电阻和分布电容的设置，分析了电路中输出电流、输出电压和死时间的变化情况。